74LS74 7474 Dual JK Flip-Flop DIP-14

74LS74 Dual JK Flip-Flop

Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs.

General Description
This device contains two independent positive-edge-trig-gered D flip-flops with complementary outputs. The infor-mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.